1. Technical Field
The invention relates generally to logic circuits. In particular, the invention relates to a logic circuit design which masks two classes of faults by the use of redundant circuits and interconnects.
2. Background Art
As integrated circuits for logic become ever large and more complex, usually as a result of further minaturization of individual elements, it has become increasingly difficult to produce perfectly operating logic circuits at an acceptable yield. As the dimensions for the electrical components on the integrated chip have become ever smaller, the processing margins have decreased. In the past, the margins were sufficiently large that an acceptable yield of perfect chips has been obtained. This acceptable yield is becoming increasingly difficult to obtain. Furthermore, noise margins have been correspondingly decreasing. That is, logic chip may operate satisfactorily a majority of the time but occasionally a noise transient is randomly impressed upon one of the internal lines and an incorrect logic operation results.
As a result, increasing attention has been devoted to error correcting logic, both for the hard failures of the exceeded processing margins and for the soft failures of the transient noise failures.
It is believed that a large fraction of failures are associated, not with the logic functions themselves, but instead with the interconnections between separated active devices. Internal logic signals often need to be conveyed relatively long distances. If there are a large number of such internal logic signal interconnections, the chip designer attempts to make the interconnection pathways as dense as possible. That is, the interconnections, typically of metal, are made relatively narrow and are separated from neighboring interconnections by minimum distances. There are several dominant failure modes for these interconnections. An interconnection can become separated somewhere in the middle so that the input to the following logic stage sees an open circuit, that is, a floating potential. Another common failure mode is that two neighboring interconnections are shorted together. In many types of logic, when two wires carrying different signals are shorted together, one logic level will dominate over the other. Thus, in the only significant logic combination in this failure mode in which one wire carries a high logic signal and the other carries a low logic signal, a short will produce a predetermined logic signal, for instance a high logic signal in many important technologies. A third common failure mode is where the metal interconnection shorts to a fixed potential, usually a high potential. This failure mode is particularly important when a subtractive etch or reactive ion etching is used to obtain fine metal interconnections.
One technique for masking faults is the use of a triple modular redundancy (TMR). Applying TMR to interconnection faults will require that each interconnection be replaced by three interconnections. Then, at the input to logic block, there would be an error correcting input stage. This error correcting input stage would compare the signals on all three of the interconnections and use as an error corrected output whatever signal is indicated on at least two of the interconnections. That is, there would be a vote between the three redundant wires. In triple modular redundancy there is the assumption that there is only a single fault so that only a single error can be corrected. This single error assumption is common in most error correcting techniques. Triple modular redundancy, although very effective, entails a substantial trade-off in chip design. Tripling the number of interconnections would, of course, require tripling the amount of chip area devoted to the long interconnections. It may be better to, instead, use a single interconnection of lower density to achieve an acceptable reliability without TMR. The area problem becomes even more severe if the triple modular redundancy is extended to include the logic function that the interconnections are driving. Take the example of a two-input logic function, with each input being driven by a long interconnection. For a combined TMR design, there are two sets of three redundant lines. The two sets of three lines are combined in all possible combinations in separate logic circuits and the vote is performed on the output of the logic circuit. However, this approach requires that there be nine logic circuits. Needless to say, this entails a very heavy price in chip area.